1. Field of the Invention
The present invention relates to a semiconductor device, a semiconductor memory device, and a method of manufacturing a semiconductor device. More particularly, the present invention relates to a dynamic random access memory (DRAM) formed on an SOI (Silicon-On-Insulator) substrate, and a method of manufacturing thereof.
2. Description of the Background Art
Many semiconductor memory devices called DRAMs are now provided. Such a DRAM requires a storage holding operation (referred to as refresh operation hereinafter), and allows data read out and writing.
FIG. 26 schematically shows a cross-sectional view of a memory cell of a conventional DRAM. Referring to FIG. 26, this memory cell includes one transfer gate transistor (referred to as transistor hereinafter) TR formed of an MOSFET and one memory capacitor (referred to as capacitor hereinafter) C.
Transistor TR includes a pair of N type source/drain regions 20 formed on the surface of a P type semiconductor substrate 100, and a transfer gate electrode 1 formed on the surface of semiconductor substrate 100 with a gate insulation film 100 thereunder. Transfer gate electrode 1 forms word line WL.
Capacitor C includes a capacitor lower electrode (referred to as storage node hereinafter) 51 connected to one of source/drain regions 20, and a capacitor upper electrode (referred to as cell plate hereinafter) 52 formed on lower electrode 51 with a dielectric layer 53 therebetween.
A bit line BL is connected to the other source/drain region 20 in transistor TR.
In the above-described memory cell of a DRAM, charge is stored in capacitor C from bit line BL via transistor TR to store data.
In recent years, transistor technology utilizing an SOI structure is being established. Such a transistor of an SOI structure is characterized in that wiring-substrate capacitance, i.e. wiring capacitance, is reduced, and the operating rate of circuitry is improved. The application of such a transistor into a CMOS provides the advantage of preventing the latch up phenomenon. There are also various advantages such as reduction of the short channel effect of the transistor, and improvement of the current driving capability and the sub threshold characteristics.
Application of an SOI structure into a memory cell of a DRAM is now in research.
However, there was the problem that a refresh operation must be carried out frequently in a conventional DRAM. This problem will be described in detail hereinafter.
A refresh operation is carried out for reasons set forth in the following. A memory cell includes a P type region and an N type region in a semiconductor substrate 100. Leakage current is generated in the junction between the P type region and the N type region. Such a leakage current causes reduction in the stored charge of a memory cell to result in loss of the stored data.
Generation of a leakage current will be described with reference to an equivalent circuit diagram of a memory cell.
FIG. 27 is an equivalent circuit diagram of the memory cell of FIG. 26. Referring to FIG. 27, a memory cell includes a transistor TR and a capacitor C.
Transistor TR is provided between a bit line BL and capacitor C. Transistor TR is turned on/off in response to the potential on word line WL. The node between transistor TR and capacitor C is a storage node 51. Capacitor C receives a cell plate potential Vcp at its cell plate.
In the proximity of the portion where storage node 51 is connected to source/drain region 20 of FIG. 26, a diode D is formed since the N type region and a P type region are connected. Diode D has its cathode connected to storage node 51 to receive a substrate potential VBB at its anode. When charge is stored in capacitor C, the leakage current at the reverse bias of diode D causes the stored charge to be reduced, resulting in loss of data.
FIG. 28 is a graph showing a change in potential V of storage node 51 in a memory cell of the DRAM shown in FIGS. 26 and 27.
The graph of FIG. 28 has potential V plotted along the ordinate, and time t plotted along the abscissa.
Referring to FIG. 28, data of an H level which is the power supply potential Vcc level is initially present due to the stored charge in the memory cell when the stored information towards the memory cell attains an H level. This potential V of storage node 51 is reduced over time according to the leakage current of the memory cell. The memory cell initially storing data of an H level has the charge gradually reduced to an L level if a refresh operation is not carried out.
Potential V falls from the level of Vcc to become lower than Vcc/2.
When reduction in potential V is encountered, a refresh operation must be carried out at a time point of tREF1 where the potential level is higher than the level of Vcc/2 by a predetermined level .DELTA.V corresponding to a sense amplifier detection capability.
Thus, execution of a refresh operation is indispensable in a conventional DRAM. The cycle of executing a refresh operation (corresponding to rREF1) must be increased to simplify control in a DRAM.